Data Cube Systems

Need a fast hard drive? The throughput on the new Seagate Technologies Barracuda XT hard drive is capable of transferring the contents of a CD in one second. The drive is based on the SATA3 standard, which doubles the predominantly used STA2s 3GBS throughput. Sporting a 64mb cache, as opposed to the 16 or 32mb in most existing drives, in order to optimize burst performance, and an areal density of 368 GB per square inch, the XT must be installed in a computer having a SATA3 controller to take advantage of the increased speed.

Seagate notes that the drive is fully backward compatible with legacy SATA controllers. SATA and SATA2 have throughputs of 1.5gbps and 3gbps, respectively. The quoted speeds are theoretical ones; in actual used, due to software and hardware overheads, real-world throughput speeds are more on the order of 200mpbs. Actual transfer rates of SATA3 should be around 600mbps. The 3.5 inch, 7200 rpm drive lists for $299 and is available as of today in North America.

It will suck up 9.23 watts of power and put out 2.9 bels of noise while seeking. Designed for desktops for high-end gamers and developers of multimedia, low cost servers, and networked storage devices. Although not available yet, add-on SATA3 expansion card controllers for existing computers are coming soon. First-generation SATA devices operated at best a little faster than parallel ATA/133 devices. Subsequently, a 3 Gbit/s signaling rate was added to the physical layer (PHY layer), effectively doubling maximum data throughput from 150 MB/s to 300 MB/s. For mechanical hard drives, SATA 3 Gbit/s transfer rate is expected to satisfy drive throughput requirements for some time, as the fastest mechanical drives barely saturate a SATA 1.5 Gbit/s link. A SATA data cable rated for 1.5 Gbit/s will handle current mechanical drives without any loss of sustained and burst data transfer performance. However, high-performance flash drives are approaching SATA 3 Gbit/s transfer rate. Given the importance of backward compatibility between SATA 1.5 Gbit/s controllers and SATA 3 Gbit/s devices, SATA 3 Gbit/s autonegotiation sequence is designed to fall back to SATA 1.5 Gbit/s speed when in communication with such devices.

In practice, some older SATA controllers do not properly implement SATA speed negotiation. Affected systems require the user to set the SATA 3 Gbit/s peripherals to 1.5 Gbit/s mode, generally through the use of a jumper, however some drives lack this jumper. Chipsets known to have this fault include the VIA VT8237 and VT8237R southbridges, and the VIA VT6420, VT6421A and VT6421L standalone SATA controllers. SiS’s 760 and 964 chipsets also initially exhibited this problem, though it can be rectified with an updated SATA controller ROM.

Intel’s plan to improve the PC’s performance and power efficiency by putting a chunk of flash memory cache on motherboards was previewed at the 2006 IDF under the codename “Robson,” and when it was launched the next year as “Turbo Memory” it never took off. Now the company has a followup to Turbo Memory, codenamed “Braidwood,” that will debut in the new 5-series chipsets for Nehalem. Braidwood’s ability to cache frequently used data, like application binaries and open files, will significantly decrease boot and load times, and provide users with a more responsive computing experience.

Why didn’t Turbo Memory take off, and why will Braidwood be any different? And is a recent, widely cited report by Objective Analysis correct in asserting that Braidwood will nullify any advantages that SSDs offer, thereby killing the latter?

From Robson to Braidwood

Turbo Memory was a good idea in theory, but it was a bit ahead of its time. The Robson flash module had to use the PCIe bus via a bridge chip, and since it was situated as far from main memory and the CPU as the hard drive, it didn’t confer a substantial average latency advantage over cache-equipped hard drives for most usage scenarios. This reality, plus Microsoft’s general lack of interest in developing software support for Robson beyond the initial lackluster Readyboost implementation, ultimately spelled doom for the technology.

But the idea of somehow wedging a large pool of flash memory into the giant latency gap in the storage hierarchy that exists between DRAM and the hard disk is still a solid one for reasons of performance and power, so Intel is having another go at it with Braidwood. Instead of relying on the PCIe bus, Braidwood will put its cache modules on a dedicated ONFi2 bus that hangs directly off the main hub. This next-gen, high-bandwidth flash interface format from Intel, which we’ve described in a previous article, is much more appropriate for hosting the flash pool than Intel’s previous bridged PCIe solution.

Braidwood will still sit the same number of hops away from DRAM and the CPU as the hard disk, so it will have to rely on a combination of the ONFi interface and latest flash modules’ much higher read/write speeds to be a useful addition to the storage hierarchy. It’s also the case that at rumored sizes of 4, 16, and 32GB, the Braidwood pool will be large enough to host a very high percentage of a system’s most-used data, which means that HDD accesses will be much rarer than under Robson.

As for the idea of Braidwood making SSDs irrelevant, the report leaves us unconvinced. It’s likely that Braidwood will cannibalize some amount of potential SSD sales, but SSDs have their own advantages (reliability, speed, power) and the main barrier to their wider adoption is their persistent price premium. What’s more likely is that the reverse will happen, and SSDs with a dedicated ONFi interface will replace Braidwood eventually. After all, it’s not clear that the majority of users are going to want to pay for 16GB of flash that they can’t directly control like a normal file volume. Besides, we just need to stop hobbling SSD with drivers and interfaces that were designed for rotating magnetic storage, and give the technology its own bus and its own dedicated role in OS memory management.

As for when Braidwood will launch, that’s still up in the air. We contacted Intel and were told, “Braidwood schedules are under assessment, we have no announcements at this time.” Recent rumors have it delayed until 2010, which would make sense in light of other rumors that Intel is developing all of the drivers and other software to make it work. Whatever the case may be, at some point the 5 series will see the addition of this technology.

The 5-series as a milestone

Tuesday’s launch of Intel’s 5-series chipset and desktop Nehalem represents the most important change in Intel’s desktop PC architecture in over a decade, because the memory controller will finally make the jump onto the processor die; in the Havendale Nehalem variant, the IGP will jump onto the die, as well. The fact that the main processor die will go from being a multicore CPU to a full-blown SoC—complete with an I/O interface in the form of PCIe links—makes the 5 series the perfect time to tackle the long-overdue task of rethinking PC system architecture based on a new storage hierarchy that presumes the availability of cheap flash memory.

In the case of Havendale, the rethink is especially apt, because with this platform, both the CPU and the GPU—the two main consumers of bandwidth in the system—are now together and are only two hops (SATA, then DMI) away from the main storage pool. This reduction of hops from three to two would, by itself, be an improvement, but adding the Braidwood cache to the mix helps even more. Most of the read/write traffic can now happen between solid state parts (DRAM and flash) via the on-die memory interface, with the magnetic disk spinning up very infrequently.

Finally, no discussion of the 5-series would be complete without noting that AMD got there first. AMD has had an on-die northbridge (and a real system interconnect, HyperTransport) since 2003, so Intel is super late to this particular party. But better late than never.

There’s no shortage of ways to perform calculations without a standard electronic computer. But the latest in a long line of weird computers runs calculations on nothing more than air.

The complicated nest of channels and valves  made by Minsoung Rhee and Mark Burns at the University of Michigan, Ann Arbor, processes binary signals by sucking air out of tubes to represent a 0, or letting it back in to represent a 1.

A chain of such 1s and 0s flows through the processor’s channels, with pneumatic valves controlling the flow of the signals between channels.

Valve computer

Each pneumatic valve is operated by changing the air pressure in a small chamber below the air channel, separated from the circuit by a flexible impermeable membrane. When the lower chamber is filled with air the membrane pushes upwards and closes the valve, preventing the binary signal flowing across one of the processor’s junctions.

Sucking out the air from the chamber reopens the valve by forcing the membrane downwards, letting the signal move across the junction.

The two researchers used the valve-controlled channels to produce a variety of logic gates, flip-flops and shift registers, which they linked together to create a working 8-bit microprocessor. That means that the longest discrete pieces of data it can handle are eight binary digits long, like the processors used in 1980s consoles such as the Nintendo Entertainment System.

It’s even possible to watch the pneumatic components in action, because the valve membranes reflect light strongly whenever they are forced downwards.

Lab helper

But the air processor is far from just being a computational curiosity, say Rhee and Burns: it has the potential to improve the “lab-on-a-chip” devices tipped to automate complex chemistry tasks and improve disease testing, DNA profiling and other lab jobs.

These pocket-scale microfluidic devices are yet to be much practical use, say the Michigan team, perhaps because they typically require a large number of bulky and expensive off-chip components to control their operation.

Using logic circuits is one way to bring most of those controls onto the lab-on-a-chip itself and reduce running costs. But because many microfluidic systems have no electronic components, adding standard electronic valves to the device would require a new fabrication process, says Burns.

“Many microfluidic systems use pneumatic valves to control liquid flow, so adding the pneumatic control circuits should be relatively simple and inexpensive,” he says.

Although the device still requires an off-chip vacuum source to operate, the volume of the microprocessor is so small that the required vacuum can be generated by a hand pump.

Versatile approach

Andrew de Mello, a microfluidics expert at Imperial College London, UK, thinks that the simplified method of operation could lead to useful microfluidic devices for developing countries.

“The fact that you can generate that vacuum from a hand pump means these devices are low power, and suited for remote locations,” he says.

However, the device is unlikely to have applications beyond its use in microfluidics – the “air” or “vacuum” signals are very sluggish compared with the lightning-quick flow of electrons through a standard circuit.

“Shrinking the device would mean that the signals would travel shorter distances and thus operate at higher ‘clock speeds’,” says Burns.

Nvidia CEO Jen-Hsun Huang has predicted that GPU computing will experience a rapid performance boost over the next six years. According to Huang, GPU compute is likely to increase its current capabilities by 570x, while ‘pure’ CPU performance will progress by a limited 3x.

Huang - who made his comments at the Hot Chips symposium in Stanford University - explained that such advances could enable the development of realtime universal language translation devices and advanced forms of augmented reality.

Huang also discussed a number of “real-world” GPU applications, including energy exploration, interactive ray tracing and CGI simulations.

In addition, Jen-Hsun fielded a number of questions at the end of the keynote speech, including a query submitted by Professor David Patterson of UC Berkley. Patterson asked if the CEO would still partition the CPU and GPU into separate chips if he had to “do it all over again.”

Huang answered that there were three primary constituents: programmers, OEMs/ODMs and chip designers. He explained that each had various requirements which made it difficult to “bet on” the integration of new and very rapidly developing architectures into one device. As such, separating the functions actually allowed each to develop at its own pace, while providing the flexibility to address multiple market opportunities.

Advanced Micro Devices has launched a low-power version of its six-core Opteron processor in time for VMworld, a key virtualization show that opens on Monday. 

The six-core AMD Opteron EE consumes 40 watts, and is designed for 2P servers, among the most popular in the virtualized server space. The chip will cost $989, and will begin shipping on Monday.

To maintain the same thermal envelope as the previous generation chip, the Opteron 2419 EE runs at 1.8 GHz, versus the 2.0+ GHz clock speeds of the “Shanghai” Opteron generation. AMD claims that the 2419 EE offers up to a third more performance than the 2377 EE, a four-core chip whose cores were clocked at 2.3 GHz, which also ran at a 40-watt thermal envelope.

The new six-core chip also includes the AMD-V virtualization technology, as AMD’s AMD-P power management mechanisms. VMworld, the show run by virtualization company VMware, begins Monday in San Francisco.

AMD also estimated that the power consumption for a fully populated 42U rack would be 9.2 KW using the six-core Opteron 2425 HE, a 55-W part. Replacing those chips with the 2419 EE would require 7.5 KW, about an 18 percent power savings.

According to IDC data quoted by Brent Kerby, a product manager for the chip, about 82 percent of cloud and Web servers only use about half of their available processor power at any given time. “With more cores, you have more headroom for those peaky times…to support a heavy amount of Web hits, if you will,” Kerby said. “The most concerning area is power consumption, being down in the the 40-watt power band, and not extending above the power threshold.”

The bottom line? More computing power in a given rack (or higher compute density) while maintaining a low 40-watt power band, Kerby said.

The new Opteron chip also uses DDR-2 memory, which AMD claimed could save about $1,000 per server, as opposed to more expensive DDR-3 memory.